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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
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CMOS/ EEPROM/ EPROM Technologies on a Single Device - Mask-ROM Devices for High-Volume Production - One-Time-Programmable (OTP) EPROM Devices for Low-Volume Production - Reprogrammable-EPROM Devices for Prototyping Purposes Internal System Memory Configurations - On-Chip Program Memory Versions - ROM: 4K or 8K Bytes - EPROM: 8K Bytes - Data EEPROM: 256 Bytes - Static RAM: 256 Bytes Usable as Registers Flexible Operating Features - Low-Power Modes: STANDBY and HALT - Commercial, Industrial, and Automotive Temperature Ranges - Clock Options - Divide-by-1 (2 MHz - 5 MHz SYSCLK) PLL - Divide-by-4 (0.5 MHz - 5 MHz SYSCLK) - Supply Voltage (VCC) 5 V 10% 16-Bit General-Purpose Timer - Software Configurable as a 16-Bit Event Counter, or a 16-Bit Pulse Accumulator, or a 16-Bit Input Capture Function, or Two Compare Registers, or a Self-Contained Pulse-Width-Modulation (PWM) Function - Software Programmable Input Polarity - 8-Bit Prescaler, Providing a 24-Bit Real-Time Timer On-Chip 24-Bit Watchdog Timer - Mask-ROM Devices: Hard Watchdog, Simple Counter, or Standard Watchdog Flexible Interrupt Handling Serial Peripheral Interface (SPI) Serial Communications Interface 1 (SCI1) TMS370 Series Compatibility - Register-to-Register Architecture - 128 or 256 General-Purpose Registers - 14 Powerful Addressing Modes - Instructions Upwardly Compatible With All TMS370 Devices
FN AND FZ PACKAGES ( TOP VIEW )
RESET C0 B4 B3 B2 B1 B0 SCITXD SCIRXD SCICLK D5 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 A2 A1 A0 D7 D4 D3 D6 NC B5 B6 B7
INT1 INT2 INT3 VCC NC A7 A6 VSS A5 A4 A3
MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT NC SPISOMI SPISIMO SPICLK NC
JC, JD, N AND NJ PACKAGES ( TOP VIEW )
B2 B3 B4 C0 RESET INT1 INT2 INT3 VCC A7 A6 VSS A5 A4 A3 A2 A1 A0 D7 D4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 B1 B0 SCITXD SCIRXD SCICLK D5 MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT SPISOMI SPISIMO SPICLK B7 B6 B5 D6 D3
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CMOS/ TTL Compatible I / O Pins / Packages - All Peripheral Function Pins Software Configurable for Digital I / O - 33 Bidirectional Pins, 1 Input Pin - 44-Pin Plastic and Ceramic Leaded Chip Carrier (LCC) Packages - 40-Pin Plastic and Ceramic Dual-In-Line (DIP) Packages Workstation / PC-Based Development System - C Compiler and C Source Debugger - Real-Time In-Circuit Emulation - Extensive Breakpoint / Trace Capability - Multi-Window User Interface - Microcontroller Programmer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
Pin Descriptions
PIN NAME A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 C0 D3 D4 D5 D6 D7 INT1 INT2 INT3 T1IC/CR T1PWM T1EVT SPISOMI SPISIMO SPICLK SCITXD SCIRXD SCICLK RESET DIP (40) 18 17 16 15 14 13 11 10 39 40 1 2 3 23 24 25 4 21 20 35 22 19 6 7 8 31 30 29 28 27 26 38 37 36 5 PLCC (44) 20 19 18 17 16 15 13 12 44 1 2 3 4 26 27 28 5 23 22 40 24 21 7 8 9 36 35 34 32 31 30 43 42 41 6 TYPE DESCRIPTION
I/O
Port A pins are general-purpose bidirectional I/O ports.
I/O
Port B pins are general-purpose bidirectional I/O ports.
I/O
Port C pin is a general-purpose bidirectional I/O port.
I/O
Port D pins are general-purpose bidirectional I/O ports. D3 is also configurable as SYSCLK.
I I/O I/O I/O
External interrupt (non-maskable or maskable) general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin Timer 1 input-capture/counter-reset input pin/general-purpose bidirectional pin Timer 1 pulse width modulation output pin/general-purpose bidirectional pin Timer 1 external event-input pin/general-purpose bidirectional pin SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin SCI transmit data output pin/general-purpose bidirectional pin SCI receive data input pin/general-purpose bidirectional pin SCI bidirectional serial clock pin/general-purpose bidirectional pin System reset bidirectional pin; as input, RESET initializes microcontroller; as open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit. Mode control-input pin. MC enables the EEPROM write-protection override (WPO) mode and EPROM VPP. Internal oscillator crystal input/external clock source input Internal oscillator output for crystal Positive supply voltage Ground reference
I/O
I/O
I/O
MC XTAL2/CLKIN XTAL1 VCC VSS NC
34 33 32 9 12 - - - -
39 38 37 10 14 11 25 29 33
I I O
No connections
I = input, O = output The three-pin configuration SCI is referred to as SCI1.
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
functional block diagram
INT1 INT2 INT3 XTAL1 XTAL2/ CLKIN MC RESET
Interrupts
Clock Options: Divide-By-4 or Divide-By-1 (PLL)
System Control
CPU
RAM 256 Bytes
Serial Communications Interface 1 Serial Peripheral Interface Timer 1
SCIRXD SCITXD SCICLK SPISOMI SPISIMO SPICLK T1IC/CR T1EVT T1PWM
Program Memory ROM: 4K or 8K Bytes EPROM: 8K Bytes
Data EEPROM 256 Bytes
Watchdog VCC VSS
Port A
Port B
Port C
Port D
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8
1
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
description
The TMS370C020A, TMS370C022A, TMS370C320A, TMS370C322A, TMS370C722, and SE370C722 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx2x refers to these devices. The TMS370 family provides cost-effective real-time system control through integration of advanced peripheral modules and various function on-chip memory configurations. The TMS370Cx2x family uses high-performance silicon-gate CMOS EPROM and EEPROM technology. Low operating power, wide operating temperature range, and noise immunity of CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the TMS370Cx2x devices attractive in system designs for automotive electronics, industrial motor, computer peripheral controls, telecommunications, and consumer applications. All TMS370Cx2x devices contain the following on-chip peripheral modules:
D D D D
Serial peripheral interface (SPI) Serial communications interface 1 (SCI1) One 24-bit general-purpose watchdog (WD) timer One 16-bit general-purpose timer with an 8-bit prescaler
Table 1 lists memory configurations of the TMS370Cx2x devices. Table 1. Memory Configurations
DEVICE PROGRAM MEMORY (BYTES) ROM 4K EPROM -- DATA MEMORY (BYTES) RAM 256 EEPROM 256 PIN/PACKAGES 44/FN-PLCC 40/N-DIP 40/NJ-PSDIP 44/FN-PLCC 40/N-DIP 40/NJ-PSDIP 44/FN-PLCC 40/N-DIP 40/NJ-PSDIP 44/FN-PLCC 40/N-DIP 40/NJ-PSDIP 44/FN-PLCC 40/N-DIP 40/NJ-PSDIP 44/FZ-CLCC 40/JD-CDIP 40/JC-CSDIP
TMS370C020A
TMS370C022A
8K
--
256
256
TMS370C320A
4K
--
256
--
TMS370C322A
8K
--
256
--
TMS370C722
--
8K
256
256
SE370C722
--
8K
256
256
System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized. The NJ designator for the 40-pin plastic shrink DIP package was formerly known as N2. The mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.
The suffix letter A appended to the device names in Table 1 indicates the configuration of the devices. ROM or EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A are configured through a programmable contact during manufacture.
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TMS370Cx2x 8-BIT MICROCONTROLLER
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description (continued)
Table 2. Suffix Letter Configuration
DEVICE EPROM without A ROM A WATCHDOG TIMER Standard Standard Hard Simple Refer to the "device numbering conventions" section for device nomenclature and the "device part numbers" section for ordering. Divide-by-4 or Divide-by-1 (PLL) Enabled or disabled CLOCK Divide-by-4 (Standard oscillator) LOW-POWER MODE Enabled
The 4K bytes and 8K bytes of mask-programmable ROM in the TMS370C020, TMS370C022, TMS370C320, and TMS370C322 are replaced in the TMS370C722 and SE370C722 with 8K bytes of EPROM. All other available memory and on-chip peripherals are identical, except there are no data EEPROMs on the TMS370C320 and TMS370C322 devices. OTP (TMS370C722) devices and the reprogrammable device (SE370C722) are available. TMS370C722 (OTP) devices are in plastic packages. This microcontroller is effective to use for immediate production updates for other members of the TMS370Cx2x family or for low-volume production runs when the mask charge or cycle time for the low-cost mask ROM devices is not practical. The SE370C722 has a windowed ceramic package to allow reprogramming of the program EPROM memory during the prototyping phase of design. These SE370C722 devices allow quick updates to breadboards and prototype systems while creating multiple initial designs. The TMS370Cx2x family provides two low-power modes (STANDBY and HALT) for applications where low power consumption is critical. Both modes stop all central processing unit (CPU) activity (that is, no instructions are executed). In the STANDBY mode, the internal oscillator, the general-purpose timer, and the SCI receiver start-bit detection remain active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes. The TMS370Cx2x features advanced register-to-register architecture that allows arithmetic and logical operations without requiring an accumulator (e.g., ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx2x family is fully instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller family. The SPI provides a convenient method of serial interaction for high speed communications between simpler shift-register type devices, such as display drivers, analog-to-digital (A/D) converter, PLL, I/O expansion, or other microcontrollers in the system. The TMS370Cx2x devices have two operational modes of serial communications provided by the SCI1 module. The SCI1 allows standard RS-232-C communications with other common data transmission equipment. The TMS370Cx2x family provides the system designer with an economical, efficient solution to real-time control applications. The TMS370 family extended development system (XDSTM) and compact development tool (CDTTM) meet the challenge of efficiently developing the software and hardware required to design the TMS370Cx2x into complex applications. The application source code can be written in assembly and C language, and the output code can be generated by the linker. The TMS370 family XDS development tool communicates through a standard RS-232-C interface with a personal computer. This allows the use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family XDS emphasizes ease-of-use through extensive menus and screen windowing so that a system designer can begin developing software with minimal training. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as a reduced time-to-market cycle.
XDS and CDT are trademarks of Texas Instruments Incorporated.
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
central processing unit (CPU)
The TMS370Cx2x device uses the high-performance 8-bit TMS370 CPU module. The 'x2x uses an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete 'x2x instruction map is shown in Table 17 in the instruction set overview section. The '370Cx2x CPU architecture provides the following components:
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CPU registers: - - - A stack pointer that points to the last entry in the memory stack A status register that monitors the operation of the instructions and contains the global interrupt-enable bits A program counter that points to the memory location of the next instruction to be executed
D
Memory blocks: - - - - 256-byte general-purpose RAM that can be used for data memory storage, program instructions, general purpose register, or the stack A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and EEPROM / EPROM programming control 256-byte EEPROM module, that provides in-circuit programmability and data retention in power-off conditions 4K- or 8K-byte ROM or 8K-byte EPROM
Figure 1 illustrates the CPU registers and memory blocks.
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central processing unit (CPU) (continued)
15 Program Counter Legend: C=Carry N=Negative Z=Zero V=Overflow IE2=Level 2 interrupts Enable IE1=Level 1 interrupts Enable 0000h 256-Byte RAM (0000h-00FFh) 0001h 0002h 0003h R1(B) R2 R3 Reserved Peripheral File Reserved 256-Byte Data EEPROM Not Available 007Fh R127 8K-Byte ROM/EPROM (6000h - 7FFFh) 6FFFh 7000h 4K-Byte ROM (7000h - 7FFFh) Interrupts and Reset Vectors; Trap Vectors 7FBFh 7FC0h 7FFFh 00FFh 0100h 0FFFh 1000h 10FFh 1100h 1EFFh 1F00h 1FFFh 2000h 5FFFh 6000h 0
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Stack Pointer (SP)
0
Status Register (ST) C 7 N 6 Z 5 V 4 IE2 IE1 3 2 1 0
RAM (Includes up to 256-Byte Registers File) 0000h R0(A)
R255 00FFh Reserved means the address space is reserved for future expansion. Not available means the address space is not accessible.
Figure 1. Programmer's Model stack pointer (SP) The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read / write memory. Typically the stack is used to store the return address on subroutine calls as well as the status register contents during interrupt sequences. The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the on-chip RAM. status register (ST) The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits.
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The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use the status bits to determine program flow. The two interrupt-enable bits control the two interrupt levels.
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TMS370Cx2x 8-BIT MICROCONTROLLER
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central processing unit (CPU) (continued)
The ST, status-bit notation, and status-bit definitions are shown in Table 3. Table 3. Status Registers
AA A AAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AA A A A A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A
7 6 5 4 3 2 1 0 C N Z V IE2 IE1 Reserved Reserved RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R = read, W = write, 0 = value after reset
program counter (PC)
The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.
During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the PC. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of the reset vector.
Program Counter (PC) Memory 0000h PCH 60 PCL 00
7FFEh 7FFFh
60 00
Figure 2. Program Counter After Reset
memory map
The TMS370Cx2x architecture is based on the Von Neuman architecture, where the program memory and data memory share a common address space. All peripheral input / output is memory mapped in this same common address space. As shown in Figure 3, the TMS370Cx2x provides memory-mapped RAM, ROM, EPROM, data EEPROM, I / O pins, peripheral functions, and system-interrupt vectors. The peripheral file contains all I / O port control, peripheral status and control, EEPROM, EPROM, and system-wide control functions. The peripheral file is located between 1010h to 105Fh and is divided logically into five peripheral file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed.
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memory map (continued)
0000h 256-Byte RAM (Register File/Stack) 00FFh 0100h 0FFFh 1000h Peripheral File 10FFh 1100h Reserved 1EFFh 1F00h 256-Byte Data EEPROM 1FFFh 2000h Not Available 5FFFh 6000h 8K-Byte 6FFFh 7000h 7FFFh 8000h Not Available FFFFh Program Memory (ROM/EPROM) Vectors Trap 15-0 Reserved Reserved Serial Communication Interface TX Serial Communication Interface RX Timer 1 Serial Peripheral Interface Interrupt 3 Interrupt 2 Interrupt 1 Reset Reserved means the address space is reserved for future expansion. Not available means the address space is not accessible. 7FC0h - 7FDFh 7FECh - 7FEDh 7FEEh - 7FEFh 7FF0h - 7FF1h 7FF2h - 7FF3h 7FF4h - 7FF5h 7FF6h - 7FF7h 7FF8h - 7FF9h 7FFAh - 7FFBh 7FFCh - 7FFDh 7FFEh - 7FFFh Reserved System Control Digital Port Control SPI Control Timer 1 Control SCI1 Control Reserved 1000h - 100Fh 1010h - 101Fh 1020h - 102Fh 1030h - 103Fh 1040h - 104Fh 1050h - 105Fh 1060h - 10FFh
Reserved
Figure 3. TMS370Cx2x Memory Map RAM/ register file (RF) Locations within the RAM address space can serve as the RF, general-purpose read / write memory, program memory, or stack instructions. The TMS370Cx2x contains 256 bytes of internal RAM mapped beginning at location 0000h (R0) and continuing through location 00FFh (R255). The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset. peripheral file (PF) The TMS370Cx2x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or P for a decimal designator. For example, the system-control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4 shows the TMS370Cx2x PF address map.
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
peripheral file (PF) (continued) Table 4. TMS370Cx2x Peripheral File Address Map
A A AAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA
ADDRESS RANGE 1000h - 100Fh 1010h - 101Fh 1020h - 102Fh 1030h - 103Fh 1040h - 104Fh 1050h - 105Fh PERIPHERAL FILE DESIGNATOR P000 - P00F P010 - P01F P020 - P02F P030 - P03F P040 - P04F P050 - P05F DESCRIPTION Reserved System and EPROM / EEPROM control registers Digital I / O port control registers SPI peripheral control registers Timer 1 registers Reserved SCI1 peripheral control registers 1060h - 10FFh P060 - P0FF
data EEPROM
The TMS370Cx2x devices contain 256 bytes of data EEPROM and are memory mapped beginning at location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the TMS370 Family User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). The data EEPROM features include the following:
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Programming: - - - - Bit-, byte-, and block-write / erase modes Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame beginning at location P01A. See Table 5. In-circuit programming capability. There is no need to remove the device to program it.
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Write protection. Writes to the data EEPROM are disabled during the following conditions. - - - Reset. All programming of the data EEPROM module is halted. Write protection active. There is one write-protect bit per 32-byte EEPROM block. Low-power mode operation
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Write protection can be overridden by applying 12 V to MC. Table 5. Data EEPROM and Program EPROM Control Registers Memory Map
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AAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A
ADDRESS P01A P01B SYMBOL DEECTL -- EPCTL NAME Data EEPROM Control Register Reserved P01C Program EPROM Control Register
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TMS370Cx2x 8-BIT MICROCONTROLLER
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program EPROM
The TMS370C722 and SE370C722 devices contain 8K bytes of program EPROM mapped, beginning at location 6000h and continuing through location 7FFFh, as shown in Figure 3. Reading the program EPROM modules is identical to reading other internal memory. During programming, the program EPROM is controlled by the EPROM control register (EPCTL). The program EPROM module features include:
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Programming - - In-circuit programming capability if VPP is applied to MC Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in the peripheral file (PF) frame at location P01C as shown in Table 5.
D
Write protection: Writes to the program EPROM are disabled under the following conditions: - - - Reset: All programming to the EPROM module is halted Low-power modes 13 V not applied to MC
program ROM
The program ROM consists of 4K or 8K bytes of mask programmable read-only memory (see Table 6). The program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication. Table 6. Program ROM Memory Map
'x20A ROM size Memory mapped 4K bytes 7000h - 7FFFh 'x22A 8K bytes 6000h - 7FFFh
system reset The system-reset operation ensures an orderly start-up sequence for the TMS370Cx2x CPU-based device. Three actions can cause a system reset. Two of these actions are internally generated, while one (RESET) is controlled externally. These actions are as follows:
D D D
Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370 Family User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B) for more information. Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See the TMS370 Family User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B) for more information. External RESET Pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the TMS370 Family User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B) for more information.
Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the 'x2x device to reset external system components. Additionally, if a cold start (VCC is off for several hundred milliseconds) condition or oscillator failure occurs or RESET pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active.
Memory addresses 7FF0h through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh.
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TMS370Cx2x 8-BIT MICROCONTROLLER
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system reset (continued) After a reset, the program can check the oscillator fault flag, the cold start flag and the watchdog reset to determine the source of the reset. A reset does not clear these flags. Table 7 lists the reset sources. Table 7. Reset Sources
AAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAA
REGISTER SCCR0 SCCR0 ADDRESS 1010h 1010h PF BIT NO. 7 4 5 CONTROL BIT COLD START SOURCE OF RESET Cold (power-up) P010 P010 OSC FLT FLAG Oscillator out of range T1CTL2 104Ah P04A WD OVRFL INT FLAG Watchdog timer timeout
Once a reset is activated, the following sequence of events occurs:
1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).
2. Registers A and B are initialized to 00h (no other RAM is changed). 3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL. 4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH. 5. Program execution begins with an opcode fetch from the address pointed to by the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state.
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interrupts
The TMS370 family software-programmable interrupt structure supports flexible on-chip and external-interrupt configurations to meet real-time interrupt-driven application requirements. The hardware-interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be enabled independently by the global-interrupt enable bits (IE1 and IE2) of the status register. Each system interrupt is configured independently on either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is configured selectively on either the high- or low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority chains is performed within the peripheral modules to support interrupt expansion to future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions. The TMS370Cx2x has seven hardware system interrupts (plus RESET) as shown in Table 8. Each system interrupt has a dedicated interrupt vector located in program memory through which control is passed to the interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXNT has two interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or for determining which interrupt source generated the associated system interrupt.
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TMS370Cx2x 8-BIT MICROCONTROLLER
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interrupts (continued)
EXT INT 3
INT 3 EXT INT 2
TIMER 1 INT3 PRI Overflow Compare1 Ext Edge Compare2 Input Capture 1
INT 2
INT2 PRI EXT INT1 CPU INT1 NMI
Watchdog
T1 PRI
INT1 PRI STATUS REG IE1
Priority Logic
Level 1 INT IE2 Level 2 INT SCI1 INT TX RX SPI INT SPI PRI Enable
TXPRI TXRDY
RXPRI BRKDT RXRDY SPI
Figure 4. Interrupt Control Four of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and therefore should be configured during the initialization sequence following reset. To maximize pin flexibility, external interrupts INT2 and INT3 can be software configured as general-purpose input/output pins if the interrupt function is not required (INT1 can be similarly configured as an input pin).
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interrupts (continued)
Table 8. Hardware System Interrupts
INTERRUPT SOURCE External RESET Watchdog Overflow Oscillator Fault Detect External INT1 External INT2 External INT3 SPI RX/TX Complete Timer 1 Overflow Timer 1 Compare 1 Timer 1 Compare 2 Timer 1 External Edge Timer 1 Input-Capture Watchdog Overflow SCI RX Data Register Full SCI RX Break Detect INTERRUPT FLAG COLD START WD OVRFL INT FLAG OSC FLT FLAG INT1 FLAG INT2 FLAG INT3 FLAG SPI INT FLAG T1 OVRFL INT FLAG T1C1 INT FLAG T1C2 INT FLAG T1EDGE INT FLAG T1IC INT FLAG WD OVRFL INT FLAG RXRDY FLAG BRKDT FLAG SYSTEM INTERRUPT RESET INT1 INT2 INT3 SPIINT VECTOR ADDRESS 7FFEh, 7FFFh 7FFCh, 7FFDh 7FFAh, 7FFBh 7FF8h, 7FF9h 7FF6h, 7FF7h PRIORITY
1 2 3 4 5
T1INT
7FF4h, 7FF5h
6
RXINT TXINT
7FF2h, 7FF3h 7FF0h, 7FF1h
7 8
SCI TX Data Register Empty TXRDY FLAG Relative priority within an interrupt level. Releases microcontroller from STANDBY and HALT low-power modes. Releases microcontroller from STANDBY low-power mode.
privileged operation and EEPROM write-protection override
The TMS370Cx2x family enables the designer to software-configure the system and peripherals to meet the requirements of a broad variety of applications. The non-privileged mode of operation ensures the integrity of the system configuration once defined for an end application. Following a hardware reset, the TMS370Cx2x operates in the privileged mode where all peripheral file registers have unrestricted read/write access and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1, causing the device to enter the non-privileged mode, thus disabling write operations to specific configuration control bits within the peripheral file. The system configuration bits listed in Table 9 are write-protected during the non-privileged mode and must be configured by software prior to exiting the privileged mode.
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TMS370Cx2x 8-BIT MICROCONTROLLER
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privileged operation and EEPROM write-protection override (continued)
Table 9. Privileged Bits
REGISTER NAME SCCR0 SCCR1 LOCATION P010.5 P010.6 P011.2 P011.4 P012.0 P012.1 P012.3 P012.4 P012.6 P012.7 P05F.4 P05F.5 P05F.6 P05F.6 P04F.6 P04F.7 P03F.5 P03F.6 P03F.7 CONTROL BIT PF AUTO WAIT OSC POWER MEMORY DISABLE AUTOWAIT DISABLE PRIVILEGE DISABLE INT1 NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY SCI ESPEN SCI RX PRIORITY SCI TX PRIORITY SCI STEST T1 PRIORITY T1 STEST SPI ESPEN SPI PRIORITY SPI STEST
SCCR2
SCIPRI
T1PRI
SPIPRI
The privileged bits are shown in a bold typeface in Table 11.
The WPO mode provides an external hardware method of overriding the WPR of data EEPROM on the TMS370Cx2x. WPO mode is entered by applying a 12-V input to the MC pin after the RESET pin input goes high. The high voltage on the MC pin during the WPO mode is not the programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware system level capability to modify the personality or calibration information in the data EEPROM while the device remains in the application, but only while a 12-V external input is present on the MC pin (normally not available in the end application except in a service or diagnostic environment).
low-power operating modes
The TMS370Cx2x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact when the mask is manufactured. The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN / IDLE bit in SCCR2 has been set to 1. The HALT / STANDBY bit in SCCR2 controls the low-power mode selection. In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity stops; however, the oscillator, internal clocks, timer 1, and receive start-bit detection circuit of the SCI1 remain active. System processing is suspended until a qualified interrupt (hardware RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the SCI1) is detected. In the HALT mode (HALT / STANDBY = 1), the TMS370Cx2x is in its lowest power consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, INT3, or low level on the receive pin of the SCI1) is detected. The power-down mode-selection bits are summarized in Table 10.
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low-power operating modes (continued)
Table 10. Low-Power/Idle Control Bits
POWER-DOWN CONTROL BITS PWRDWN/IDLE (SCCR2.6) 1 1 0 Don't care HALT/STANDBY (SCCR2.7) 0 1 X MODE SELECTED STANDBY HALT IDLE
When low-power modes are disabled through a programmable contact, writing to the SCCR2.6-7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled, the device always enters the IDLE mode. To provide a method for always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This means that the NMI always is generated, regardless of the interrupt enable flags. The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file), CPU registers (SP, PC, and ST), I / O pin direction and output data, and status registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking of the WD timer is inhibited.
clock modules
The 'x2x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 MCU. The 'x2x masked ROM devices offer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. The divide-by-1 clock module option provides reduced electromagnetic interference (EMI) with no added cost. The divide-by-1 provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system clock (SYSCLK) frequency, whereas the divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency. These are formulated as follows:
+ external resonator frequency + CLKIN 4 4 external resonator frequency 4 Divide-by-1 option : SYSCLK + + CLKIN 4
Divide-by-4 option : SYSCLK The main advantage of a divide-by-1 oscillator is the improved EMI performance. The harmonics of low-speed resonators extend through fewer of the emissions spectrum than the harmonics of faster resonators. The divide-by-1 reduces the resonator speed by four, and this results in a steeper decay of emissions produced by the oscillator.
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TMS370Cx2x 8-BIT MICROCONTROLLER
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system configuration registers
Table 11 contains peripheral file frame 1 system configuration and control register functions for controlling EEPROM programming. The privileged bits are shown in bold typeface and shaded. Table 11. Peripheral File Frame 1: System Configuration and Control Registers
PF P010 P011 P012 P013 to P016 P017 P018 P019 P01A P01B P01C P01D P01E P01F Privileged bits are shown in bold typeface. BUSY VPPS -- -- Reserved INT1 FLAG INT2 FLAG INT3 FLAG BUSY INT1 PIN DATA INT2 PIN DATA INT3 PIN DATA -- -- -- -- -- -- INT2 DATA DIR INT3 DATA DIR -- Reserved -- -- W0 EXE EPCTL BIT 7 COLD START -- HALT/ STANDBY BIT 6 OSC POWER -- PWRDWN/ IDLE BIT 5 PF AUTO WAIT -- -- BIT 4 OSC FLT FLAG AUTOWAIT DISABLE BUS STEST BIT 3 MC PIN WPO -- CPU STEST Reserved INT1 POLARITY INT2 POLARITY INT3 POLARITY AP INT1 PRIORITY INT2 PRIORITY INT3 PRIORITY W1W0 INT1 ENABLE INT2 ENABLE INT3 ENABLE EXE BIT 2 MC PIN DATA MEMORY DISABLE -- BIT 1 -- -- INT1 NMI BIT 0 P/C MODE -- PRIVILEGE DISABLE REG SCCR0 SCCR1 SCCR2
-- INT2 DATA OUT INT3 DATA OUT --
INT1 INT2 INT3 DEECTL
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peripheral file frame 2
Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 12 and Table 13 detail the specific addresses, registers, and control bits within the peripheral file frame. Table 12. Peripheral File Frame 2: Digital Port Control Registers
PF P020 P021 P022 P023 P024 P025 P026 P027 P028 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Reserved Port A Control Register 2 (must be 0) Port A Data Port A Direction Reserved Port B Control Register 2 (must be 0) Port B Data Port B Direction Reserved Port C Control Register 2 (must be 0) Port C Data Port C Direction -- -- -- -- BIT 2 BIT 1 BIT 0 APORT1 APORT2 ADATA ADIR BPORT1 BPORT2 BDATA BDIR CPORT1
P029
--
--
--
--
--
--
--
CPORT2
P02A P02B P02C P02D P02E P02F
-- --
-- --
-- --
-- --
-- --
-- -- -- -- -- --
-- -- -- -- -- --
CDATA CDIR DPORT1 DPORT2 DDATA DDIR
Port D Control Register 1 (must be 0) Port D Control Register 2 (must be 0) Port D Data Port D Direction To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
Table 13. Port Configuration Register Setup
PORT A B C D PIN 0-7 0-7 0 3-7 abcd 00q1 Data out q Data out q Data out q Data out q a = Port x Control Register 1 b = Port x Control Register 2 c = Data d = Direction abcd 00y0 Data in y Data in y Data in y Data in y
DPORT only
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TMS370Cx2x 8-BIT MICROCONTROLLER
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programmable timer 1
The programmable timer module of the TMS370Cx2x provides the enhanced timer resources required to perform real-time system control. The Timer 1 module contains the general-purpose timer T1 and the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock sources (real-time, external event, or pulse-accumulate) with multiple 16-bit registers (input-capture and compare) for special timer function control. The timer 1 module includes three external device pins that can be used for multiple counter functions (operation-mode dependent), or used as general-purpose I/O pins. The T1 module is shown in Figure 5.
T1IC/CR
Edge Select
16-Bit Capt/Comp Register
MUX
16-Bit Counter
16
PWM Toggle
T1PWM
16-Bit Compare Register T1EVT 8-Bit Prescaler
Interrupt Logic
Interrupt Logic
MUX
16-Bit Watchdog Counter (Aux. Timer)
Figure 5. Timer 1 Block Diagram
D
Three T1 I/O pins - - - T1IC/CR: T1 input capture / counter-reset input pin, or general-purpose bidirectional I/O pin T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin
D D D D D D
Two operational modes: - - Dual-compare mode: Provides PWM signal Capture/compare mode: Provides input capture pin
One 16-bit general-purpose resettable counter One 16-bit compare register with associated compare logic One 16-bit capture/compare register, which, depending on the mode of operation, operates as either capture or compare register One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if WD feature is not needed. Prescaler/clock sources that determine one of eight clock sources for general-purpose timer
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programmable timer 1 (continued)
D D
Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T1IC/CR) Interrupts that can be generated on the occurrence of: - - - - A capture A compare equal A counter overflow An external edge detection
D
Sixteen T1 module control registers located in the PF frame beginning at address P040
The T1 module control registers are listed in Table 14.
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AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA A AAA AA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAA A AAA AA A AAA AA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAA A A A A A A A A A AAA AA AAA A AAA AA A AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAA AA AAA A AAA AA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA AAAA A A A A A A A A A AAA AA AAA A AAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A A AAA AA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAA
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
TMS370Cx2x 8-BIT MICROCONTROLLER
22 P04D P04C P04C P04E P04B P04B P04A P04F P049 P048 Bit 7 P047 Bit 7 P046 Bit 15 P045 Bit 7 P044 Bit 15 P043 Bit 7 P042 Bit 15 P041 Bit 7 P040 Bit 15 PF Mode: Capture / Compare Mode: Dual-Compare WD OVRFL RST ENA WD OVRFL TAP SEL T1 MODE = 1 T1 STEST T1EDGE INT FLAG T1EDGE INT FLAG T1 MODE=0 T1PWM DATA IN BIT 7 -- WD OVRFL INT ENA WD INPUT SELECT2 T1PWM DATA OUT T1 PRIORITY T1C2 INT FLAG T1C1 OUT ENA T1C1 OUT ENA BIT 6 -- --
programmable timer 1 (continued)
Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored.
Modes: Dual-Compare and Capture / Compare
Modes: Dual-Compare and Capture / Compare
Table 14. Timer Module Register Memory Map
WD OVRFL INT FLAG
T1PWM FUNCTION
WD INPUT SELECT1
T1C1 INT FLAG
T1C1 INT FLAG
T1C2 OUT ENA
BIT 5
Capture/Compare Register MSbyte
Capture/Compare Register LSbyte
--
--
--
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Watchdog Counter MSbyte
Compare Register MSbyte
Watchdog Counter LSbyte
Compare Register LSbyte
Watchdog Reset Key
T1 Counter LSbyte
T1Counter MSbyte
WD INPUT SELECT0
T1 OVRFL INT ENA
T1PWM DATA DIR
T1C1 RST ENA
T1C1 RST ENA
BIT 4
--
--
--
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T1 OVRFL INT FLAG T1CR OUT ENA T1IC/CR DATA IN T1EVT DATA IN BIT 3 -- -- -- -- -- T1EDGE POLARITY T1EDGE POLARITY T1EVT DATA OUT T1IC/CR DATA OUT T1 INPUT SELECT2 T1EDGE INT ENA T1EDGE INT ENA BIT 2 -- -- T1EVT FUNCTION T1IC/CR FUNCTION T1 INPUT SELECT1 T1CR RST ENA T1C2 INT ENA BIT 1 -- -- -- -- T1 SW RESET T1EVT DATA DIR T1IC/CR DATA DIR T1 INPUT SELECT0 T1EDGE DET ENA T1EDGE DET ENA T1C1 INT ENA T1C1 INT ENA BIT 0 -- Bit 8 T1C Bit 8 T1CC Bit 8 WDCNTR Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 WDRST Bit 8 T1CNTR T1PRI REG T1PC2 T1PC1 T1CTL4 T1CTL3 T1CTL4 T1CTL3 T1CTL2 T1CTL1
TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
programmable timer 1 (continued)
Figure 6 shows the Timer 1 capture/compare mode block diagram. The annotations on the diagram identify the register and the bit(s) in the PF. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.
T1CC.15-0
16-Bit LSB Capt/Comp MSB Register T1C1 OUT ENA
T1CTL4.6
Toggle
Prescale Clock Source
T1PC2.7-4
T1PWM
T1CNTR.15-0
LSB 16-Bit MSB Counter 16 T1 PRIORITY Compare= Reset
T1CTL3.5 T1CTL3.0
T1 SW RESET
T1C.15-0
T1C1 RST ENA 16-Bit LSB Compare Register MSB
T1C1 INT ENA
T1CTL2.0
T1CTL4.4
T1 OVRFL INT FLAG T1CTL2.3
T1CTL2.4
T1 OVRFL INT ENA
T1PC2.3-0
T1EDGE DET ENA T1IC/CR Edge Select T1EDGE INT FLAG
T1CTL3.7 T1CTL4.0 T1CTL3.2 T1CTL4.2
T1EDGE POLARITY T1EDGE INT ENA
Figure 6. Capture/Compare Mode
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IIII
T1PRI.6
T1C1 INT FLAG
0 1
Level 1 Int Level 2 Int
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TMS370Cx2x 8-BIT MICROCONTROLLER
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programmable timer 1 (continued)
Figure 7 shows the Timer 1 dual-compare mode block diagram. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.
T1CC.15-0
16-Bit LSB Capt/Comp Register MSB T1C2 INT FLAG
Prescaler Clock Source
T1CTL3.6 T1CTL3.1 T1C2 INT ENA
Output Enable
T1CNTR.15-0
LSB MSB 16-Bit Counter Reset T1 SW RESET T1C1 RST ENA
Compare=
T1CTL4.5 T1PC2.7-4
T1C2 OUT ENA
16 Compare=
Toggle
T1C1 INT FLAG T1CTL3.5
T1CTL4.6
T1C1 OUT ENA
T1PWM
T1C.15-0
16-Bit LSB Compare Register MSB
T1CTL3.0
T1C1 INT ENA
T1CTL4.3
T1CR OUT ENA
T1CTL2.0
T1CTL4.4
T1 OVRFL INT FLAG
T1PC2.3-0
T1IC/CR
T1CTL4.1 T1CR RST ENA
Edge Select
T1CTL2.3 T1CTL2.4
T1 OVRFL INT ENA T1 PRIORITY
T1CTL4.0 T1EDGE DET ENA T1CTL4.2 T1EDGE POLARITY
T1EDGE INT FLAG
T1PRI.6
0 1
Level 1 Int Level 2 Int
T1CTL3.7 T1CTL3.2
T1EDGE INT ENA
Figure 7. Dual-Compare Mode
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TMS370Cx2x 8-BIT MICROCONTROLLER
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programmable timer 1 (continued)
The TMS370Cx2x device includes a 24-bit WD timer, contained in the T1 module, which can be programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not used. The WD monitors software and hardware operation, and implements a system reset when the WD counter is not serviced properly (WD counter overflow or WD counter is re-initialized by an incorrect value). The WD can be configured as one of the three mask options as follows: standard watchdog, hard WD, or simple counter.
D
Standard watchdog configuration (see Figure 8) for 'C722 EPROM and mask-ROM devices: - Watchdog mode - - - - - Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK A WD reset key (WDRST) register clears the watchdog counter (WDCNTR) when a correct value is written. Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter overflows A watchdog overflow flag (WD OVRFL INT FLAG) bit indicates whether the WD timer initiated a system reset.
Non-watchdog mode - Watchdog timer can be configured as an event counter, pulse accumulator or an interval timer.
WDCNTR.15-0
16-Bit Watchdog Counter WD OVRFL INT FLAG
T1CTL2.6
Interrupt WD OVRFL INT ENA
T1CTL2.5
Reset
Clock Prescaler
T1CTL1.7
WD OVRFL TAP SEL Watchdog Reset Key
T1CTL2.7
System Reset WD OVRFL RST ENA
WDRST.7-0
Figure 8. Standard Watchdog
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TMS370Cx2x 8-BIT MICROCONTROLLER
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programmable timer 1 (continued)
D
Hard watchdog configuration (see Figure 9) for 'C722 EPROM and mask-ROM devices: - - - - - - Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK A WD reset key (WDRST) register clears the watchdog counter (WDCNTR) when a correct value is written. Generates a system reset if an incorrect value is written to the WDRST or if the counter overflows A WD overflow flag (WD OVRFL INT FLAG) bit indicates whether the WD timer initiated a system reset. Automatic activation of the WD timer upon power-up reset INT1 is enabled as a nonmaskable interrupt during low power modes.
WDCNTR.15-0
16-Bit Watchdog Counter WD OVRFL INT FLAG
T1CTL2.5
Reset
Clock Prescaler
T1CTL1.7
WD OVRFL TAP SEL Watchdog Reset Key System Reset
WDRST.7-0
Figure 9. Hard Watchdog
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TMS370Cx2x 8-BIT MICROCONTROLLER
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programmable timer 1 (continued)
D
Simple counter configuration (see Figure 10) for mask-ROM devices only - Simple counter can be configured as an event counter, pulse accumulator, or internal timer.
WDCNTR.15-0
16-Bit Watchdog Counter WD OVFL INT FLAG
T1CTL2.6
Interrupt WD OVRFL INT ENA
T1CTL2.5
Reset
Clock Prescaler
T1CTL1.7
WD OVRFL TAP SEL Watchdog Reset Key
WDRST.7-0
Figure 10. Simple Counter
serial peripheral interface
The SPI is a high-speed synchronous serial I/O port that allows a serial bit stream of programmed length (1 to 8 bits) to be shifted into and out of the device at a programmable bit transfer rate. The SPI normally is used for communications between the microcontroller and external peripherals or another microcontroller. Typical applications include external I/O or peripheral expansion by way of devices such as shift registers, display drivers, and A/D converters. Multi-device communications are supported by the master/slave operation of the SPI. The SPI module features include the following:
D
Three external pins - - - SPISOMI: SPI slave output/master input pin or general-purpose bidirectional I/O pin SPISIMO: SPI slave input/master output pin or general-purpose bidirectional I/O pin SPICLK: SPI serial clock pin or general-purpose bidirectional I/O pin
D D
Two operational modes: Master and slave Eight programmable baud rates - Maximum baud rate in master mode: 2.5M bps at 5 MHz SYSCLK SPI BAUD RATE
+ SYSCLK 22
b
where b=bit rate in SPICCR.5-3 (range 0-7) - Maximum baud rate in slave mode: 625K bps at 5 MHz SYSCLK SPI BAUD RATE < SYSCLK / 8
D D
Data word format: one to eight data bits Simultaneous receiver and transmitter operations (transmit function can be disabled in software)
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TMS370Cx2x 8-BIT MICROCONTROLLER
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serial peripheral interface (continued)
D D
Transmitter and receiver operations occur through interrupt-driven or polled algorithms. Seven SPI module control registers located in control register frame beginning at address P030h
The SPI module control registers are listed in Table 15. Table 15. SPI Module Control Register Memory Map
AA A AAA A AAAA AAAA A A A A A AAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A A AAAA A AAA AAA AA A AAA AA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AAA AA A AAAA A A A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A A A AAAA AA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAA AAAA A A A A A A A AAAA A A AAAA A A A A A A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A AAAA A A AAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA
PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG P030 P031 P032 to P036 P037 P038 P039 SPI SW RESET CLOCK POLARITY SPI INT FLAG SPI BIT RATE2 -- SPI BIT RATE1 -- SPI BIT RATE0 -- SPI CHAR2 SPI CHAR1 TALK SPI CHAR0 SPICCR SPICTL RECEIVER OVERRUN MASTER/ SLAVE SPI INT ENA Reserved RCVD7 SDAT7 RCVD6 SDAT6 RCVD5 SDAT5 RCVD4 SDAT4 RCVD3 SDAT3 RCVD2 SDAT2 RCVD1 SDAT1 RCVD0 SDAT0 SPIBUF SPIDAT Reserved P03A to P03C P03D Reserved -- -- -- -- SPICLK DATA IN SPICLK DATA OUT SPICLK FUNCTION SPICLK DATA DIR SPIPC1 SPIPC2 SPIPRI P03E SPISIMO DATA IN SPI STEST SPISIMO DATA OUT SPI PRIORITY SPISIMO FUNCTION SPI ESPEN SPISIMO DATA DIR -- SPISOMI DATA IN -- SPISOMI DATA OUT -- SPISOMI FUNCTION -- SPISOMI DATA DIR -- P03F 28
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serial peripheral interface (continued)
The SPI block diagram is listed in Figure 11.
SPIBUF.7-0
SPIBUF Buffer Register RECEIVER OVERRUN
SPICTL.7
8 SPI INT FLAG
SPIPRI.6 SPICTL.0
0 1 SPIINT ENA
Level 1 INT Level 2 INT
SPICTL.6
SPIDAT Data Register
SPIPC2.7-4
SPISIMO
SPIDAT.7-0
SPICTL.1 SPIPC2.3-0
TALK SPISOMI
State Control
MASTER/SLAVE SPI CHAR
SPICCR.2-0
2 1 0
SPICTL.2 SPIPC1.3-0
System Clock
SPICCR.5-3
5 4 3
SPICCR.6
CLOCK POLARITY
SPICLK
SPI BIT RATE The diagram shows slave mode.
Figure 11. SPI Block Diagram
serial communications interface 1 (SCI1)
The TMS370x2x devices include a serial communications interface 1 (SCI1) module. The SCI1 module supports digital communications between the TMS370 devices and other asynchronous peripherals, and uses the standard non-return-to-zero (NRZ) format. The SCI1's receiver and transmitter are double buffered, and each has separate enable and interrupt bits. Both can operate independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity, overrun, and framing errors. The bit rate (baud) is programmable to over 65,000 speeds through a 16-bit baud-select register.
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TMS370Cx2x 8-BIT MICROCONTROLLER
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serial communications interface 1 (SCI1) (continued)
Features of the SCI1 module include:
D
Three external pins: - - - SCITXD: SCI transmit output pin or general purpose bidirectional I/O pin SCIRXD: SCI receive input pin or general purpose bidirectional I/O pin SCICLK: SCI bidirectional serial clock pin, or general purpose bidirectional I/O pin
D D
Two communications modes: asynchronous and isosynchronous Baud rate: 64K programmable rates - Asynchronous mode: 3 bps to 156K bps at 5 MHz SYSCLK ASYNCHRONOUS BAUD -
+ (BAUD SYSCLK1) REG ) + (BAUDSYSCLK 1) REG )
32
Isosynchronous mode: 39 bps to 2.5M bps at 5 MHz SYSCLK ISOSYNCHRONOUS BAUD 2
D
Data word format - - - - One start bit Data word length programmable from 1 to 8 bits Optional even/odd/no parity bit One or two stop bits
D D D D D
Four error-detection flags: parity, overrun, framing, and break detection Two wake-up multiprocessor modes: Idle-line and address bit Half or full-duplex operation Double-buffered receive and transmit functions Interrupt driven or polled algorithms with status flags control transmitter (TX) and receiver (RX) operations. - - - - Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX EMPTY flag (transmitter shift register is empty) Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR monitoring four interrupt conditions Separate enable bits for transmitter and receiver interrupts NRZ (non-return-to-zero) format
D
Eleven SCI1 module control registers are located in control register frame beginning at address P050h.
Isosynchronous = Isochronous
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serial communications interface 1 (SCI1) (continued)
The SCI1 module control registers are listed in Table 16. Table 16. Peripheral File Frame 5: SCI1 Module Control Registers
PF P050 P051 P052 P053 P054 P055 P056 P057 P058 P059 P05A P05B P05C P05D P05E P05F -- SCI TXD DATA IN SCI STEST -- SCI TXD DATA OUT SCI TX PRIORITY -- SCI TXD FUNCTION SCI RX PRIORITY -- SCI TXD DATA DIR SCI ESPEN SCICLK DATA IN SCI RXD DATA IN -- SCICLK DATA OUT SCI RXD DATA OUT -- SCICLK FUNCTION SCI RXD FUNCTION -- SCICLK DATA DIR SCI RXD DATA DIR -- SCIPC1 SCIPC2 SCIPRI Reserved BIT 7 STOP BITS -- Bit 15 Bit 7 TXRDY RX ERROR TX EMPTY RXRDY -- BRKDT BIT 6 EVEN/ODD PARITY -- BIT 5 PARITY ENABLE SCI SW RESET BIT 4 ASYNC/ ISOSYNC CLOCK BIT 3 ADDRESS IDLE WUP TXWAKE BIT 2 SCI CHAR2 SLEEP BIT 1 SCI CHAR1 TXENA BIT 0 SCI CHAR0 RXENA Bit 8 Bit 0 -- PE -- RXWAKE SCI TX INT ENA SCI RX INT ENA REG SCICCR SCICTL BAUD MSB BAUD LSB TXCTL RXCTL
Baud Rate Select Register MSB Baud Rate Select Register LSB -- FE Reserved Receive Data Buffer Register Reserved Transmit Data Buffer Register -- OE
RXBUF TXBUF
Privileged bits are shown in bold typeface.
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serial communications interface 1 (SCI1) (continued)
The SCI1 module block diagram is illustrated in Figure 12.
Frame Format and Mode PARITY EVEN / ODD ENABLE TXWAKE SCICTL.3 1 WUT 8 TX EMPTY TXCTL.6 TXENA
TXBUF.7 - 0
Transmit Data Buffer Reg. SCI TX Interrupt TXRDY TXCTL.7 SCI TX INT ENA SCITX PRIORITY
SCICCR.6 SCICCR.5
TXCTL.0
BAUD MSB. 7 - 0
Baud Rate MSbyte Reg. SYSCLK
TXSHF Reg.
SCITXD
SCICTL.1
CLOCK
BAUD LSB. 7 - 0
Baud Rate LSbyte Reg.
SCICTL.4
RXSHF Reg. RXWAKE
SCIRXD
RXCTL.1
RXENA RX ERROR
SCI RX Interrupt RXRDY RXCTL.6 SCI RX INT ENA
SCICTL.0
8 Receive Data Buffer Reg.
RXCTL.7
ERR
RXCTL.4 - 2
FE OE PE BRKDT RXCTL.5
RXCTL.0
RXBUF.7 - 0
Figure 12. SCI1 Block Diagram
instruction set overview
Table 17 provides an opcode-to-instruction cross reference of all 73 instructions and 274 opcodes of the `370Cx2x instruction set. The numbers at the top of this table represent the most significant nibble (MSN) of the opcode while the numbers at the left side of the table represent the least significant nibble (LSN). The instruction of these two opcode nibbles contains the mnemonic, operands, and byte / cycle particular to that opcode. For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles.
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IIII III III
SCIPRI.5
SCIPRI.6
0 1
Level 1 INT Level 2 INT
SCIPC2.7 - 4
SCITXD
SCIPC1.3 - 0
SCICLK
SCIPC2.3 - 0
SCIRXD
SCIRX PRIORITY 0 1 Level 1 INT Level 2 INT
Table 17. TMS370 Family Opcode/Instruction Map
MSN 0 0 JMP #ra 2/7 JN ra 2/5 JZ ra 2/5 JC ra 2/5 JP ra 2/5 JPZ ra 2/5 JNZ ra 2/5 JNC ra 2/5 JV ra 2/5 JL ra 2/5 JLE ra 2/5 JHS ra 2/5 MOV Rs,A 2/7 AND Rs,A 2/7 OR Rs,A 2/7 XOR Rs,A 2/7 BTJO Rs,A,ra 3/9 BTJZ Rs.,A,ra 3/9 ADD Rs,A 2/7 ADC Rs,A 2/7 SUB Rs,A 2/7 SBB Rs,A 2/7 MOV A,Pd 2/8 MOV #n,A 2/6 AND #n,A 2/6 OR #n,A 2/6 XOR #n,A 2/6 BTJO #n,A,ra 3/8 BTJZ #n,A,ra 3/8 ADD #n,A 2/6 ADC #n,A 2/6 SUB #n,A 2/6 SBB #n,A 2/6 MOV Rs,B 2/7 AND Rs,B 2/7 OR Rs,B 2/7 XOR Rs,B 2/7 BTJO Rs,B,ra 3/9 BTJZ Rs,B,ra 3/9 ADD Rs,B 2/7 ADC Rs,B 2/7 SUB Rs,B 2/7 SBB Rs,B 2/7 MOV Rs,Rd 3/9 AND Rs,Rd 3/9 OR Rs,Rd 3/9 XOR Rs,Rd 3/9 BTJO Rs,Rd,ra 4/11 BTJZ Rs,Rd,ra 4/11 ADD Rs,Rd 3/9 ADC Rs,Rd 3/9 SUB Rs,Rd 3/9 SBB Rs,Rd 3/9 MOV B,Pd 2/8 MOV #n,B 2/6 AND #n,B 2/6 OR #n,B 2/6 XOR #n,B 2/6 BTJO #n,B,ra 3/8 BTJZ #n,B,ra 3/8 ADD #n,B 2/6 ADC #n,B 2/6 SUB #n,B 2/6 SBB #n,B 2/6 MOV B,A 1/8 AND B,A 1/8 OR B,A 1/8 XOR B,A 1/8 BTJO B,A,ra 2/10 BTJZ B,A,ra 2/10 ADD B,A 1/8 ADC B,A 1/8 SUB B,A 1/8 SBB B,A 1/8 1 2 3 4 5 6 7 INCW #ra,Rd 3/11 MOV Rs,Pd 3/10 MOV #n,Rd 3/8 AND #n,Rd 3/8 OR #n,Rd 3/8 XOR #n,Rd 3/8 BTJO #n,Rd,ra 4/10 BTJZ #n,Rd,ra 4/10 ADD #n,Rd 3/8 ADC #n,Rd 3/8 SUB #n,Rd 3/8 SBB #n,Rd 3/8 AND A,Pd 2/9 OR A,Pd 2/9 XOR A,Pd 2/9 BTJO A,Pd,ra 3/11 BTJZ A,Pd,ra 3/10 MOVW #16,Rd 4/13 JMPL lab 3/9 MOV & lab,A 3/10 MOV A, & lab 3/10 AND B,Pd 2/9 OR B,Pd 2/9 XOR B,Pd 2/9 BTJO B,Pd,ra 3/10 BTJZ B,Pd,ra 3/10 MOVW Rs,Rd 3/12 JMPL *Rp 2/8 MOV *Rp,A 2/9 MOV A, *Rp 2/9 8 MOV Ps,A 2/8 MOV Ps,B 2/7 MOV Ps,Rd 3/10 AND #n,Pd 3/10 OR #n,Pd 3/10 XOR #n,Pd 3/10 BTJO #n,Pd,ra 4/11 BTJZ #n,Pd,ra 4/11 MOVW #16[B],Rpd 4/15 JMPL *lab[B] 3/11 MOV *lab[B],A 3/12 MOV A,*lab[B] 3/12 DEC A 1/8 INC A 1/8 INV A 1/8 CLR A 1/8 XCHB A 1/10 SWAP A 1/11 PUSH A 1/9 POP A 1/9 DJNZ A,#ra 2/10 COMPL A 1/8 DEC B 1/8 INC B 1/8 INV B 1/8 CLR B 1/8 XCHB A / TST B 1/10 SWAP B 1/11 PUSH B 1/9 POP B 1/9 DJNZ B,#ra 2/10 COMPL B 1/8 9 A B CLRC / TST A 1/9 C MOV A,B 1/9 D MOV A,Rd 2/7 MOV B,Rd 2/7 DEC Rd 2/6 INC Rd 2/6 INV Rd 2/6 CLR Rn 2/6 XCHB Rn 2/8 SWAP Rn 2/9 PUSH Rd 2/7 POP Rd 2/7 DJNZ Rd,#ra 3/8 COMPL Rd 2/6 E TRAP 15 1/14 TRAP 14 1/14 TRAP 13 1/14 TRAP 12 1/14 TRAP 11 1/14 TRAP 10 1/14 TRAP 9 1/14 TRAP 8 1/14 TRAP 7 1/14 TRAP 6 1/14 TRAP 5 1/14 TRAP 4 1/14 IDLE 1/6 MOV #n,Pd 3/10 SETC 1/7 RTS 1/9 RTI 1/12 PUSH ST 1/8 F LDST n 2/6 MOV #ra[SP],A 2/7 MOV A,*ra[SP] 2/7 CMP *n[SP],A 2/8 extend inst,2 opcodes
1
2
3
4 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443
L S N
5
6
7
8
9
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
A
B
TMS370Cx2x 8-BIT MICROCONTROLLER
All conditional jumps (opcodes 01 - 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand.
33
Table 17. TMS370 Family Opcode/Instruction Map (Continued)
MSN 0 C JNV ra 2/5 JGE ra 2/5 JG ra 2/5 JLO ra 2/5 1 MPY Rs,A 2/46 CMP Rs,A 2/7 DAC Rs,A 2/9 DSB Rs,A 2/9 2 MPY #n,A 2/45 CMP #n,A 2/6 DAC #n,A 2/8 DSB #n,A 2/8 3 MPY Rs,B 2/46 CMP Rs,B 2/7 DAC Rs,B 2/9 DSB Rs,B 2/9 4 MPY Rs,Rd 3/48 CMP Rs,Rd 3/9 DAC Rs,Rd 3/11 DSB Rs,Rd 3/11 5 MPY #n,B 2/45 CMP #n,B 2/6 DAC #n,B 2/8 DSB #n,B 2/8 6 MPY B,A 1/47 CMP B,A 1/8 DAC B,A 1/10 DSB B,A 1/10 7 MPY #n,Rs 3/47 CMP #n,Rd 3/8 DAC #n,Rd 3/10 DSB #n,Rd 3/10 8 BR lab 3/9 CMP & lab,A 3/11 CALL lab 3/13 CALLR lab 3/15 9 BR *Rp 2/8 CMP *Rp,A 2/10 CALL *Rp 2/12 CALLR *Rp 2/14 A BR *lab[B] 3/11 CMP *lab[B],A 3/13 CALL *lab[B] 3/15 CALLR *lab[B] 3/17 B RR A 1/8 RRC A 1/8 RL A 1/8 RLC A 1/8 C RR B 1/8 RRC B 1/8 RL B 1/8 RLC B 1/8 D RR Rd 2/6 RRC Rd 2/6 RL Rd 2/6 RLC Rd 2/6 E TRAP 3 1/14 TRAP 2 1/14 TRAP 1 1/14 TRAP 0 1/14 F POP ST 1/8 LDSP 1/7 STSP 1/8 NOP 1/7
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
TMS370Cx2x 8-BIT MICROCONTROLLER
34
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Template Release Date: 7-11-94
Second byte of two-byte instructions (F4xx):
F4
8
MOVW *n[Rn] 4/15 JMPL *n[Rn] 4/16 MOV *n[Rn],A 4/17 MOV A,*n[Rn] 4/16 BR *n[Rn] 4/16 CMP *n[Rn],A 4/18 CALL *n[Rn] 4/20 CALLR *n[Rn] 4/22
DIV Rn.A 3/14-63
F4 Legend: * = Indirect addressing operand prefix & = Direct addressing operand prefix # = immediate operand #16 = immediate 16-bit number lab = 16-label n = immediate 8-bit number i di t 8 bit b Pd = Peripheral register containing destination type Pn = Peripheral register Ps = Peripheral register containing source byte Peri heral ra = Relative address Rd = Register containing destination type Rn = Register file Rp = Register pair Rpd = Destination register pair Rps = Source Register pair Rs = Register containing source byte
9
F4
A
F4
B
F4
C
F4
D
F4
E
F4
F
All conditional jumps (opcodes 01 - 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand.
TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
development system support
The TMS370 family development support tools include an assembler, a C compiler, a linker, an in-circuit emulator XDS/22, CDT, and an EEPROM / UVEPROM programmer.
D
Assembler/ linker (Part No. TMDS3740850-02 for PC) - - - Includes extensive macro capability Provides high-speed operation Includes format conversion utilities for popular formats
D
ANSI C Compiler (Part No. TMDS3740855-02 for PC, Part No. TMDS3740555-09 for HP700TM, Sun-3TM or Sun-4TM) - - - - - - Generates assembly code for the TMS370 that can be inspected easily Improves code execution speed and reduces code size with optional optimizer pass Enables direct reference the TMS370's port registers by using a naming convention Provides flexibility in specifying the storage for data objects Interfaces C functions and assembly functions easily Includes assembler and linker
D
CDT370 (Compact Development Tool) real-time in-circuit emulation - Base (Part Number EDSCDT370 - for PC, requires cable) - - - - - - - - - - Cable for 40-pin DIP (Part No. EDSTRG40DILX) Cable for 44-pin PLCC (Part No. EDSTRG44PLCCX) Cable for 40-pin SDIP (Part No. EDSTRG40SDILX)
EEPROM and EPROM programming support Allows inspection and modification of memory locations Includes compatibility to upload / download program and data memory Executes programs and software routines Includes 1 024 samples trace buffer Includes single-step executable instructions Uses software breakpoints to halt program execution at selected address
D
XDS/ 22 in-circuit emulator - - - - - Base (Part Number TMDS3762210 for PC, requires cable) Cable for 40-pin DIP / SDIP, 44-pin PLCC (Part No. TMDS3788844) Contains all of the features of the CDT370 described previously but does not have the capability to program the data EEPROM and program EPROM Contains sophisticated breakpoint trace and timing hardware that provides up to 2 047 qualified trace samples with symbolic disassembly Allows qualification of breakpoints by address and / or data on any type of memory acquisition. Up to four levels of events can be combined to cause a breakpoint.
HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Incorporated.
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TMS370Cx2x 8-BIT MICROCONTROLLER
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development system support (continued)
- - Provides timers for analyzing total and average time in routines Contains an eight-line logic probe for adding visibility of external signals to the breakpoint qualifier and to trace display
D
Microcontroller programmer - Base (Part No. TMDS3760500A - for PC, requires programmer head) - - - Single unit head for 44-pin PLCC (Part No. TMDS3780510A) Single unit head for 40-pin DIP / SDIP (Part No. TMDS3780511A)
PC-based, window / function-key-oriented user interface for ease of use and rapid learning environment
D
Starter Kit (Part No. TMDS37000 - for PC) - - - - Includes TMS370 Assembler diskette and documentation Includes TMS370 Simulator Includes programming adapter board and programming software Does not include (to be supplied by the user) - - - + 5 V power supply ZIF sockets Nine-pin RS232 cable
36
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device numbering conventions
Figure 13 illustrates the numbering and symbol nomenclature for the TMS370Cx2x family.
TMS 370 C 3 2 2 A FN L Prefix: TMS = Standard prefix for fully qualified devices SE = System evaluator (window EPROM) that is used for prototyping . Family: Technology: Program Memory Types: 370 = TMS370 8-Bit Microcontroller Family C = CMOS 0 = Mask ROM 3 = Mask ROM, No Data EEPROM 7 = EPROM 2 = 'x2x device containing the following modules: - Timer 1 - Serial Peripheral Interface - Serial Communication Interface 1 0 = 4K bytes 2 = 8K bytes A = - 40C to 85C L= 0C to 70C T = - 40C to 105C FN FZ JC JD N NJ = = = = = = Plastic Leaded Chip Carrier Ceramic Leaded Chip Carrier Ceramic Shrink Dual-In-Line Ceramic Dual-in-Line Plastic Dual-In-Line Plastic Shrink Dual-In-Line
Device Type:
Memory Size: Temperature Ranges:
Packages:
ROM and EPROM Option:
A = For ROM device, the watchdog timer can be configured as one of the three different mask options: - A standard watchdog - A hard watchdog - A simple watchdog The clock can be either: - Divide-by-4 clock - Divide-by-1 (PLL) clock The low-power modes can be either: - Enabled - Disabled None = For EPROM device, a standard watchdog, a divide-by4 clock, and low-power modes are enabled
Figure 13. TMS370Cx2x Family Nomenclature
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device part numbers
Table 18 lists all of the 'x2x devices available. The device part number nomenclature is designed to assist ordering. Upon ordering, the customer must specify not only the device part number, but also the clock and watchdog timer options desired. Each device can have only one of the three possible watchdog timer options and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices. Table 18. Device Part Numbers
DEVICE PART NUMBERS FOR 44 PINS (LCC) TMS370C020AFNA TMS370C020AFNL TMS370C020AFNT TMS370C022AFNA TMS370C022AFNL TMS370C022AFNT TMS370C320AFNA TMS370C320AFNL TMS370C320AFNT TMS370C322AFNA TMS370C322AFNL TMS370C322AFNT TMS370C722FNT SE370C722FZT DEVICE PART NUMBERS FOR 40 PINS (DIP) TMS370C020ANA TMS370C020ANL TMS370C020ANT TMS370C022ANA TMS370C022ANL TMS370C022ANT TMS370C320ANA TMS370C320ANL TMS370C320ANT TMS370C322ANA TMS370C322ANL TMS370C322ANT TMS370C722NT SE370C722JDT DEVICE PART NUMBERS FOR 40 PINS (SDIP) TMS370C020ANJA TMS370C020ANJL TMS370C020ANJT TMS370C022ANJA TMS370C022ANJL TMS370C022ANJT TMS370C320ANJA TMS370C320ANJL TMS370C320ANJT TMS370C322ANJA TMS370C322ANJL TMS370C322ANJT TMS370C722NJT
SE370C722JCT The NJ designator for the 40-pin plastic shrink DIP package was formerly known as N2. The mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified. System evaluators are for use only in prototype environment, and their reliability has not been characterized.
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TMS370Cx2x 8-BIT MICROCONTROLLER
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new code release form
Figure 14 shows a sample of the new code release form.
NEW CODE RELEASE FORM TEXAS INSTRUMENTS TMS370 MICROCONTROLLER PRODUCTS
DATE:
To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:
1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media) 2. An attached specification if not using TI standard specification as incorporated in TI's applicable device data book.
Company Name: Street Address: Street Address: City: Customer Part Number: Customer Application:
Contact Mr./Ms.: Phone: ( State Zip
)
Ext.:
Customer Purchase Order Number: Customer Print Number *Yes: # No: (Std. spec to be followed) *If Yes: Customer must provide "print" to TI w/NCRF for approval before ROM code processing starts.
TMS370 Device: TI Customer ROM Number: (provided by Texas Instruments) OSCILLATOR FREQUENCY MIN [] External Drive (CLKIN) [] Crystal [] Ceramic Resonator TYP MAX
CONTACT OPTIONS FOR THE 'A' VERSION TMS370 MICROCONTROLLERS
Low Power Modes [] Enabled [] Disabled
Watchdog counter [] Standard [] Hard Enabled [] Simple Counter
Clock Type [] Standard (/4) [] PLL (/1)
[] Supply Voltage MIN: (std range: 4.5V to 5.5V)
MAX:
NOTE: Non 'A' version ROM devices of the TMS370 microcontrollers will have the "Low-power modes Enabled", "Divide-by-4" Clock, and "Standard" Watchdog options. See the TMS370 Family User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). PACKAGE TYPE [] 'N' 28-pin PDIP [] "FN" 44-pin PLCC [] "FN" 28-pin PLCC [] "FN" 68-pin PLCC [] "N" 40-pin PDIP [] "NM" 64-pin PSDIP [] "NJ" 40-pin PSDIP (formerly known as N2) BUS EXPANSION [] YES [] NO
TEMPERATURE RANGE [] 'L': 0 to 70C (standard) [] 'A': -40 to 85C [] 'T': -40 to 105C SYMBOLIZATION [] TI standard symbolization [] TI standard w/customer part number [] Customer symbolization (per attached spec, subject to approval)
NON-STANDARD SPECIFICATIONS: ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material (i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a 'P' in the symbolization preceding the TI part number.
RELEASE AUTHORIZATION: This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification code is approved by the customer.
1. Customer:
Date:
2. TI: Field Sales: Marketing: Prod. Eng.: Proto. Release:
Figure 14. Sample New Code Release Form
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
Table 19 is a collection of all the peripheral file frames used in the 'Cx2x (provided for a quick reference). Table 19. Peripheral File Frame Compilation
AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A A A AAAA AAAA AA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A AAAA A AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A A A AAA AA AAA A AAA AA AAA AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA AAAA A A A A A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA AAAAA AAAA AAA AAAA AAAA AAAA A A AAAA AAA A A AAAA AA AAAAA A AAAA AAAA A AAAA A AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAA A A A AAAA A AAAAAAAAAAA AAAAA AAAAAAAAAAAAAA AAAAAAAAAA AAAAA A A AAAAAAA A AAA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAA AAAAAAAAAAAAAAAAAAAAA AAAA AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A A AAAA AAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A AAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAA
PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG System Configuration Registers OSC FLT FLAG MC PIN WPO -- P010 COLD START -- OSC POWER -- PF AUTO WAIT -- MC PIN DATA -- P / C MODE -- SCCR0 P011 AUTO WAIT DISABLE BUS STEST MEMORY DISABLE -- -- SCCR1 P012 P013 to P016 P017 P018 P019 HALT / STANDBY PWRDWN / IDLE -- CPU STEST INT1 NMI PRIVILEGE DISABLE SCCR2 Reserved INT1 FLAG INT2 FLAG INT3 FLAG INT1 PIN DATA INT2 PIN DATA INT3 PIN DATA -- -- -- -- -- -- -- INT1 POLARITY INT2 POLARITY INT3 POLARITY AP INT1 PRIORITY INT2 PRIORITY INT3 PRIORITY W1W0 INT1 ENABLE INT2 ENABLE INT3 ENABLE EXE INT1 INT2 INT3 INT2 DATA DIR INT3 DATA DIR -- INT2 DATA OUT INT3 DATA OUT -- P01A P01B BUSY DEECTL Reserved P01C P01D P01E P01F BUSY VPPS -- -- -- -- W0 EXE EPCTL Reserved Digital Port Control Registers Reserved P020 P021 P022 P023 P024 P025 P026 P027 P028 P029 P02A P02B P02C P02D P02E P02F -- -- -- -- -- -- -- -- -- -- -- -- APORT1 APORT2 ADATA ADIR BPORT1 BPORT2 BDATA BDIR CPORT1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Port C Control Register 2 (must be 0) Port C Data Port C Direction -- -- -- -- CPORT2 CDATA CDIR DPORT1 DPORT2 DDATA DDIR Port A Control Register 2 (must be 0) Port A Data Port A Direction Reserved Port B Control Register 2 (must be 0) Port B Data Port B Direction Reserved Port D Control Register 1 (must be 0) Port D Control Register 2 (must be 0) Port D Data Port D Direction
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA
To configure pin D3 as SYSCLK, set port D control register 2 = 08h. 40
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AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A AA AAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA AAA AAA AA AA AA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A AA AAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA A A AAA AAA A A A A AA AAA AA AAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AAA AA AAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA AA A AAAA A A A A A A A AAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A AAA A A AAAA A A A A A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A AAA AAA A A A A A A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA AA AA AA AAA AA AA
P04C P04C P03D P03A to P03C P04B P04B P04A P03E P03F P049 P048 P047 P046 P045 P044 P043 P042 P041 P040 P039 P038 P037 P032 to P036 P031 P030 PF
Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored.
Mode: Capture / Compare
Mode: Dual-Compare
Bit 7
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Modes: Dual-Compare and Capture / Compare
T1 MODE=0
WD OVRFL RST ENA
WD OVRFL TAP SEL
RECEIVER OVERRUN
T1 MODE = 1
T1EDGE INT FLAG
T1EDGE INT FLAG
SPISIMO DATA IN
SPI SW RESET
RCVD7
SPI STEST
SDAT7
BIT 7
--
WD OVRFL INT ENA
CLOCK POLARITY
WD INPUT SELECT2
SPISIMO DATA OUT
SPI PRIORITY
T1C2 INT FLAG
T1C1 OUT ENA
T1C1 OUT ENA
SPI INT FLAG
RCVD6
SDAT6
BIT 6
--
--
Table 19. Peripheral File Frame Compilation (Continued)
WD OVRFL INT FLAG
SPISIMO FUNCTION
WD INPUT SELECT1
T1C1 INT FLAG
T1C1 INT FLAG
T1C2 OUT ENA
SPI BIT RATE2
SPI ESPEN
RCVD5
SDAT5
BIT 5
Capture/Compare Register MSbyte
Capture/Compare Register LSbyte
--
--
--
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SPI Module Control Register Memory Map
Watchdog Counter MSbyte
Compare Register MSbyte
Watchdog Counter LSbyte
Compare Register LSbyte
Timer Module Register Memory Map
Watchdog Reset Key
T1 Counter LSbyte
T1Counter MSbyte
WD INPUT SELECT0
T1 OVRFL INT ENA
SPISIMO DATA DIR
T1C1 RST ENA
T1C1 RST ENA
SPI BIT RATE1
RCVD4
SDAT4
BIT 4
--
--
--
--
--
Reserved
Reserved
Reserved
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T1 OVRFL INT FLAG T1CR OUT ENA SPISOMI DATA IN SPICLK DATA IN SPI BIT RATE0 RCVD3 SDAT3 BIT 3 -- -- -- -- -- -- T1EDGE POLARITY T1EDGE POLARITY SPISOMI DATA OUT SPICLK DATA OUT T1 INPUT SELECT2 MASTER/ SLAVE T1EDGE INT ENA T1EDGE INT ENA RCVD2 SPI CHAR2 SDAT2 BIT 2 -- -- SPISOMI FUNCTION SPICLK FUNCTION T1 INPUT SELECT1 T1CR RST ENA T1C2 INT ENA SPI CHAR1 RCVD1 SDAT1 BIT 1 TALK -- -- -- -- T1 SW RESET SPICLK DATA DIR SPISOMI DATA DIR T1 INPUT SELECT0 T1EDGE DET ENA T1EDGE DET ENA T1C1 INT ENA T1C1 INT ENA SPI INT ENA RCVD0 SPI CHAR0 SDAT0 BIT 0 --
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
TMS370Cx2x 8-BIT MICROCONTROLLER
Bit 8
Bit 8
Bit 8
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
T1CTL4
T1CTL3
T1CTL4
T1CTL3
T1CTL2
T1CTL1
WDRST
WDCNTR
T1CC
T1C
T1CNTR
SPIPRI
SPIPC2
SPIPC1
SPIDAT
REG
SPICCR
SPIBUF
SPICTL
41
TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
Table 19. Peripheral File Frame Compilation (Continued)
AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAA AA A A A A A A A AAA AA A A AAA AA AAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA A AAA AA AAA
PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG Modes: Dual-Compare and Capture / Compare -- -- -- P04D P04E P04F -- T1EVT DATA IN T1EVT DATA OUT T1EVT FUNCTION T1EVT DATA DIR T1PC1 T1PC2 T1PRI T1PWM DATA IN T1PWM DATA OUT T1 PRIORITY T1PWM FUNCTION -- T1PWM DATA DIR -- T1IC/CR DATA IN -- T1IC/CR DATA OUT -- T1IC/CR FUNCTION -- T1IC/CR DATA DIR -- T1 STEST SCI1 Module Control Register Memory Map ASYNC/ ISOSYNC CLOCK ADDRESS IDLE WUP TXWAKE P050 P051 P052 P053 P054 P055 P056 P057 P058 P059 P05A P05B P05C P05D P05E P05F -- SCI TXD DATA IN SCI STEST -- SCI TXD DATA OUT SCI TX PRIORITY -- SCI TXD FUNCTION SCI RX PRIORITY -- SCI TXD DATA DIR SCI ESPEN SCICLK DATA IN SCI RXD DATA IN -- SCICLK DATA OUT SCI RXD DATA OUT -- SCICLK FUNCTION SCI RXD FUNCTION -- SCICLK DATA DIR SCI RXD DATA DIR -- SCIPC1 SCIPC2 SCIPRI Reserved STOP BITS -- EVEN/ODD PARITY -- PARITY ENABLE SCI SW RESET SCI CHAR2 SLEEP SCI CHAR1 TXENA SCI CHAR0 SCICCR SCICTL BAUD MSB BAUD LSB TXCTL RXCTL RXENA Bit 8 Bit 0 -- PE -- RXWAKE SCI TX INT ENA SCI RX INT ENA Bit 15 Bit 7 TXRDY RX ERROR TX EMPTY RXRDY -- BRKDT Baud Rate Select Register MSB Baud Rate Select Register LSB -- FE -- OE Reserved Receive Data Buffer Register Reserved Transmit Data Buffer Register TXBUF RXBUF
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAA
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range,VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 14 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current per buffer, IO (VO = 0 to VCC)) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Maximum ICC current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA Maximum ISS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 170 mA Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature, TA: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 105C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS. 2. Electrical characteristics are specified with all output buffers loaded with specified IO current. Exceeding the specified IO current in any buffer can affect the levels on other buffers.
recommended operating conditions
MIN VCC VIL Supply voltage (see Note 1) RAM data-retention supply voltage (see Note 3) Low-level Low level input voltage All pins except MC MC, normal operation All pins except MC, XTAL2 / CLKIN, and RESET VIH Hi h l li t lt High-level input voltage XTAL2 / CLKIN RESET EEPROM write protect override (WPO) VMC MC (mode control) voltage EPROM programming voltage (VPP) Microcomputer L version TA Operating free-air temperature A version T version 4.5 3 VSS VSS 2 0.8 VCC 0.7 VCC 11.7 13 VSS 0 - 40 - 40 12 13.2 NOM 5 MAX 5.5 5.5 0.8 0.3 VCC VCC VCC 13 13.5 0.3 70 85 105 C V V UNIT V V V
NOTES: 1. Unless otherwise noted, all voltage values are with respect to VSS. 3. RESET must be externally activated when VCC or SYSCLK is out of the recommended operating range.
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOL VOH Low-level output voltage High-level High level output voltage TEST CONDITIONS IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA 0 V < VI 0.3 V MC 0.3 V < VI 13 V See Note 4 12 V VI 13 V I / O pins IOL IOH Low-level output current High-level High level output current 0 V VI VCC VOL = 0.4 V VOH = 0.9 VCC VOH = 2.4 V See Notes 5 and 6 SYSCLK = 5 MHz See Notes 5 and 6 SYSCLK = 3 MHz See Notes 5 and 6 SYSCLK = 0.5 MHz See Notes 5 and 6 SYSCLK = 5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 8) See Notes 5 and 6 SYSCLK = 3 MHz See Notes 5 and 6 SYSCLK = 0.5 MHz Supply current (STANDBY mode) y ( ) OSC POWER bit = 1 (see Note 9) See Notes 5 and 6 SYSCLK = 3 MHz See Notes 5 and 6 SYSCLK = 0.5 MHz See Note 5 XTAL2 / CLKIN < 0.2 V 1.4 - 50 -2 30 20 7 10 8 2 6 2 2 45 30 11 17 11 3.5 8.6 mA 3.0 30 A mA mA MIN 0.9 VCC 2.4 10 650 50 10 TYP MAX 0.4 UNIT V V A mA A mA A mA
II
Input current
Supply current (operating mode) OSC POWER bit = 0 (see Note 7)
Supply current (HALT mode)
NOTES: 4. Input current IPP is a maximum of 50 mA only during EPROM programming. 5. Single chip mode, ports configured as inputs or outputs with no load. All inputs 0.2 V or VCC - 0.2V. 6. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 7. Maximum operating current = 7.6 (SYSCLK) + 7 mA. 8. Maximum standby current = 3 (SYSCLK) + 2 mA (OSC POWER bit = 0). 9. Maximum standby current = 2.24 (SYSCLK) + 1.9 mA (OSC POWER bit = 1, only valid up to 3 MHz SYSCLK).
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
XTAL2/CLKIN
XTAL1
XTAL2/CLKIN
XTAL1
C1 (see Note B)
Crystal/Ceramic Resonator (see Note A)
C2 (see Note B)
External Clock Signal
C3 (see Note B)
NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period. B. The values of C1 and C2 are typically 15 pF and C3 value is typically 50 pF. See the manufacturer's recommendations for ceramic resonators.
Figure 15. Recommended Crystal/Clock Connections
Load Voltage 1.2 k VO 20 pF
Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.
Figure 16. Typical Output Load Circuit (See Note A)
VCC VCC
300 30 I/O 20
Pin Data Output Enable
6 k
INT1 20
GND
GND
Figure 17. Typical Buffer Circuitry
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: AR B CI D M PGM R RXD Array Byte XTAL2/CLKIN DATA Master mode Program READ SCIRXD S SC SIMO SOMI SPC TXD W Slave mode SYSCLK SPISIMO SPISOMI SPICLK SCITXD WRITE
Lowercase subscripts and their meanings are: c d f r cycle time (period) delay time fall time rise time su v w setup time valid time pulse duration (width)
The following additional letters are used with these meanings: H L V High Low Valid
All timings are measured between high and low measurement points as indicated in Figure 18 and Figure 19.
0.8 VCC V (High) 0.8 V (Low)
2 V (High) 0.8 V (Low)
Figure 18. XTAL2/CLKIN Measurement Points
Figure 19. General Measurement Points
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TMS370Cx2x 8-BIT MICROCONTROLLER
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external clocking requirements for clock divided by 4 (see Note 10 and Figure 20)
NO. 1 2 3 4 tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency 2 PARAMETER Pulse duration, XTAL2/CLKIN (see Note 11) MIN 20 30 30 100 20 MAX UNIT ns ns ns ns MHz
SYSCLK Internal system clock operating frequency 0.5 5 MHz SYSCLK = CLKIN/4 NOTES: 10. For VIL and VIH, refer to recommended operating conditions. 11. This pulse may be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 1 XTAL2/CLKIN 2 3 4 SYSCLK
Figure 20. External Clock Timing for Divide-by-4
external clocking requirements for clock divided by 1 (PLL) (see Note 10 and Figure 21)
NO. 1 2 3 4 tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency 2 2 PARAMETER Pulse duration, XTAL2/CLKIN (see Note 11) MIN 20 30 30 100 5 5 MAX UNIT ns ns ns ns MHz
MHz SYSCLK = CLKIN/1 NOTES: 10. For VIL and VIH, refer to recommended operating conditions. 11. This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
1 XTAL2/CLKIN 2 SYSCLK 3 4
Figure 21. External Clock Timing for Divide-by-1
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
switching characteristics and timing requirements (see Note 12 and Figure 22)
NO. 5 6 7 tc tw(SCL) tw(SCH) PARAMETER Cycle time, SYSCLK (system clock) time Pulse duration, SYSCLK low Pulse duration, SYSCLK high Divide-by-4 Divide-by-1 MIN 200 200 0.5 tc-20 0.5 tc MAX 2000 500 0.5 tc 0.5 tc + 20 UNIT ns ns ns
NOTE 12: tc = system-clock cycle time = 1 / SYSCLK
5 6 SYSCLK
7
Figure 22. SYSCLK Timing
general purpose output signal switching time requirements (see Figure 23)
MIN tr tf Rise time Fall time NOM 30 30 MAX UNIT ns ns
tr tf
Figure 23. Signal Switching Timing
recommended EEPROM timing requirements for programming
MIN tw(PGM)B tw(PGM)AR Pulse duration, programming signal to ensure valid data is stored (byte mode) Pulse duration, programming signal to ensure valid data is stored (array mode) 10 20 NOM MAX UNIT ms ms
recommended EPROM operating conditions for programming
MIN VCC VPP IPP SYSCLK Supply voltage Supply voltage at MC pin Supply current at MC pin during programming (VPP = 13 V) System clock Divide-by-4 Divide-by-1 0.5 2 4.75 13 NOM 5.5 13.2 30 MAX 6 13.5 50 5 5 UNIT V V mA MHz
recommended EPROM timing requirements for programming
MIN tw(EPGM) Pulse duration, programming signal (see Note 13) NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set. 0.40 NOM 0.50 MAX 3 UNIT ms
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
SPI master mode external timing characteristics and requirements (see Note 12 and Figure 24)
NO. 38 39 40 41 42 43 44 tc(SPC)M tw(SPCL)M tw(SPCH)M td(SPCL-SIMOV)M tv(SPCH-SIMO)M tsu(SOMI-SPCH)M tv(SPCH-SOMI)M Cycle time, SPICLK Pulse duration, SPICLK low Pulse duration, SPICLK high Delay time, SPISIMO valid after SPICLK low (polarity = 1) Valid time, SPISIMO data valid after SPICLK high (polarity =1) Setup time, SPISOMI to SPICLK high (polarity = 1) Valid time, SPISOMI data valid after SPICLK high (polarity = 1) MIN 2tc tc - 45 tc - 55 - 65 tw(SPCH) - 50 0.25 tc + 150 0 MAX 256tc 0.5tc(SPC)+45 0.5tc(SPC)+45 50 UNIT ns ns ns ns ns ns ns
NOTE 12: tc = system-clock cycle time = 1 / SYSCLK 38 40 39 SPICLK 41 SPISIMO 43 44 SPISOMI Data Valid Data Valid 42
NOTE A: The diagram is for polarity = 1. SPICLK is inverted when polarity = 0.
Figure 24. SPI Master External Timing
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
SPI slave mode external timing characteristics and requirements (see Note 12 and Figure 25)
NO. 45 46 47 48 49 50 tc(SPC)S tw(SPCL)S tw(SPCH)S td(SPCL-SOMIV)S tv(SPCH-SOMI)S tsu(SIMO-SPCH)S Cycle time, SPICLK Pulse duration, SPICLK low Pulse duration, SPICLK high Delay time, SPISOMI valid after SPICLK low (polarity = 1) Valid time, SPISOMI data valid after SPICLK high (polarity =1) Setup time, SPISIMO to SPICLK high (polarity = 1) tw(SPCH)S 0 3tc + 100 MIN 8tc 4tc - 45 4tc - 45 MAX 0.5tc(SPC)S+45 0.5tc(SPC)S+45 3.25tc + 130 UNIT ns ns ns ns ns ns ns
51 tv(SPCH-SIMO)S Valid time, SPISIMO data after SPICLK high (polarity = 1) NOTE 12: tc = system-clock cycle time = 1 / SYSCLK
45 47 46 SPICLK 48 SPISIMO 50 51 SPISOMI Data Valid Data Valid 49
NOTE A: The diagram is for polarity = 1. SPICLK is inverted when polarity = 0.
Figure 25. SPI Slave External Timing
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
SCI1 isosynchronous mode timing characteristics and requirements for internal clock (see Note 12 and Figure 26)
NO. 24 25 26 27 28 29 30 tc(SCC) tw(SCCL) tw(SCCH) td(SCCL-TXDV) tv(SCCH-TXD) tsu(RXD-SCCH) Cycle time, SCICLK Pulse duration, SCICLK low Pulse duration, SCICLK high Delay time, SCITXD valid after SCICLK low Valid time, SCITXD data valid after SCICLK high Setup time, SCIRXD to SCICLK high MIN 2tc tc - 45 tc - 45 - 50 tw(SCCH) - 50 0.25 tc + 145 0 MAX 131 072tc 0.5tc(SCC)+45 0.5tc(SCC)+45 60 UNIT ns ns ns ns ns ns ns
tv(SCCH-RXD) Valid time, SCIRXD data valid after SCICLK high NOTE 12: tc = system-clock cycle time = 1 / SYSCLK 24 26 25 SCICLK 28 27 SCITXD 29 30 SCIRXD Data Valid Data Valid
Figure 26. SCI1 Isosynchronous Mode Timing for Internal Clock
Isosynchronous = Isochronous
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TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
SCI1 isosynchronous mode timing characteristics and requirements for external clock (see Note 12 and Figure 27)
NO. 31 32 33 34 35 36 37 tc(SCC) tw(SCCL) tw(SCCH) td(SCCL-TXDV) tv(SCCH-TXD) tsu(RXD-SCCH) Cycle time, SCICLK Pulse duration, SCICLK low Pulse duration, SCICLK high Delay time, SCITXD valid after SCICLK low Valid time, SCITXD data valid after SCICLK high Setup time, SCIRXD to SCICLK high tw(SCCH) 40 2tc MIN 10tc 4.25tc + 120 tc + 120 4.25tc + 145 MAX UNIT ns ns ns ns ns ns ns
tv(SCCH-RXD) Valid time, SCIRXD data after SCICLK high NOTE 12: tc = system-clock cycle time = 1 / SYSCLK 31 33 32 SCICLK 35 34 SCITXD 36 37 SCIRXD Data Valid Data Valid
Figure 27. SCI1 Isosynchronous Timing for External Clock
Isosynchronous = Isochronous
52
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
Table 20 is designed to aid the user in referencing a device part number to a mechanical drawing. The table shows a cross-reference of the device part number to the TMS370 generic package name and the associated mechanical drawing by drawing number and name. Table 20. TMS370Cx2x Family Package Type and Mechanical Cross-Reference
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PKG TYPE (mil pin spacing) TMS370 GENERIC NAME PKG TYPE NO. AND MECHANICAL NAME DEVICE PART NUMBERS FN - 44 pin (50-mil pin spacing) PLASTIC LEADED CHIP CARRIER (PLCC) FN(S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER TMS370C020AFNA TMS370C020AFNL TMS370C020AFNT TMS370C022AFNA TMS370C022AFNL TMS370C022AFNT TMS370C320AFNA TMS370C320AFNL TMS370C320AFNT TMS370C322AFNA TMS370C322AFNL TMS370C322AFNT TMS370C722FNT SE370C722FZT SE370C722JDT FZ - 44 pin (50-mil pin spacing) CERAMIC LEADED CHIP CARRIER (CLCC) FZ(S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER JD - 40 pin (100-mil pin spacing) CERAMIC DUAL-IN-LINE PACKAGE (CDIP) JD(R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE N - 40 pin (100-mil pin spacing) PLASTIC DUAL-IN-LINE PACKAGE (PDIP) N(R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE TMS370C020ANA TMS370C020ANL TMS370C020ANT TMS370C022ANA TMS370C022ANL TMS370C022ANT TMS370C320ANA TMS370C320ANL TMS370C320ANT TMS370C322ANA TMS370C322ANL TMS370C322ANT TMS370C722NT SE370C722JCT JC - 40 pin (70-mil pin spacing) CERAMIC SHRINK DUAL-IN-LINE PACKAGE (CSDIP) JC(R-CDIP-T40) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE NJ - 40 pin (70-mil pin spacing) PLASTIC SHRINK DUAL-IN-LINE PACKAGE (PSDIP) NJ(R-PDIP-T**) PLASTIC SHRINK DUAL-IN-LINE PACKAGE TMS370C020ANJA TMS370C020ANJL TMS370C020ANJT TMS370C022ANJA TMS370C022ANJL TMS370C022ANJT TMS370C320ANJA TMS370C320ANJL TMS370C320ANJT TMS370C322ANJA TMS370C322ANJL TMS370C322ANJT TMS370C722NJT NJ formerly known as N2; the mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.
POST OFFICE BOX 1443
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53
TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
MECHANICAL DATA
FN (S-PQCC-J**)
20 PIN SHOWN Seating Plane 0.004 (0,10) D D1 3 1 19 0.032 (0,81) 0.026 (0,66) 4 18 D2 / E2 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) 0.020 (0,51) MIN
PLASTIC J-LEADED CHIP CARRIER
E
E1 D2 / E2 8 14
0.050 (1,27) 9 13 0.008 (0,20) NOM
0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M
NO. OF PINS ** 20 28 44 52 68 84
D/E MIN 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 0.785 (19,94) 0.985 (25,02) 1.185 (30,10) MAX 0.395 (10,03) 0.495 (12,57) 0.695 (17,65) 0.795 (20,19) 0.995 (25,27) 1.195 (30,35) MIN
D1 / E1 MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.756 (19,20) 0.958 (24,33) 1.158 (29,41) MIN
D2 / E2 MAX 0.169 (4,29) 0.219 (5,56) 0.319 (8,10) 0.369 (9,37) 0.469 (11,91) 0.569 (14,45) 4040005 / B 03/95
0.350 (8,89) 0.450 (11,43) 0.650 (16,51) 0.750 (19,05) 0.950 (24,13) 1.150 (29,21)
0.141 (3,58) 0.191 (4,85) 0.291 (7,39) 0.341 (8,66) 0.441 (11,20) 0.541 (13,74)
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018
54
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
MECHANICAL DATA
FZ (S-CQCC-J**)
28 LEAD SHOWN 0.040 (1,02)
J-LEADED CERAMIC CHIP CARRIER
45
A B 4 1 26 0.180 (4,57) 0.155 (3,94) 0.140 (3,55) 0.120 (3,05)
Seating Plane
5
25
0.050 (1,27)
A
B
0.032 (0,81) 0.026 (0,66)
C (at Seating Plane) 0.020 (0,51) 0.014 (0,36)
11
19
12
18 0.025 (0,64) R TYP 0.040 (1,02) MIN 0.120 (3,05) 0.090 (2,29) A MIN 0.485 (12,32) 0.685 (17,40) 0.785 (19,94) 0.985 (25,02) MAX 0.495 (12,57) 0.695 (17,65) 0.795 (20,19) 0.995 (25,27) MIN 0.430 (10,92) 0.630 (16,00) 0.730 (18,54) 0.930 (23,62) B MAX 0.455 (11,56) 0.655 (16,64) 0.765 (19,43) 0.955 (24,26) MIN 0.410 (10,41) 0.610 (15,49) 0.680 (17,28) 0.910 (23,11) C MAX 0.430 (10,92) 0.630 (16,00) 0.740 (18,79) 0.930 (23,62)
JEDEC OUTLINE MO-087AA MO-087AB MO-087AC MO-087AD
NO. OF PINS** 28 44 52 68
4040219 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit.
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55
TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
MECHANICAL DATA
JC (R-CDIP-T40) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
1.414 (35,92) 1.386 (35,20) 40 21
0.600 (15,24) 0.580 (14,73)
1
20 0.032 (0,81) TYP
0.093 (2,38) 0.077 (1,96)
0.060 (1,52) 0.040 (1,02)
0.610 (15,49) 0.590 (14,99)
Seating Plane
0.020 (0,51) 0.016 (0,41) 0.070 (1,78) 1.335 (33,91) 1.325 (33,66)
0.175 (4,46) TYP
0.012 (0,31) 0.009 (0,23)
4040223-2 / B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated.
56
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
MECHANICAL DATA
JD (R-CDIP-T**)
24 PIN SHOWN A DIM 24 13 A MAX PINS **
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 1.250 (31,75)
28 1.450 (36,83)
40 2.050 (52,07)
48 2.435 (61,85)
52 2.650 (67,31)
0.590 (15,00) TYP
1 0.065 (1,65) 0.045 (1,14)
12
0.075 (1,91) MAX 4 Places
0.175 (4,45) 0.140 (3,56)
0.620 (15,75) 0.590 (14,99)
Seating Plane 0.020 (0,51) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) MIN 0- 15 0.012 (0,30) 0.008 (0,20) 4040087 / B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated.
POST OFFICE BOX 1443
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57
TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
MECHANICAL DATA
N (R-PDIP-T**)
24 PIN SHOWN A 24 13
PLASTIC DUAL-IN-LINE PACKAGE
0.560 (14,22) 0.520 (13,21)
1 0.060 (1,52) TYP
12 0.200 (5,08) MAX 0.020 (0,51) MIN
0.610 (15,49) 0.590 (14,99)
Seating Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.125 (3,18) MIN 0.010 (0,25) NOM
0- 15
PINS ** DIM A MAX
24 1.270 (32,26) 1.230 (31,24)
28 1.450 (36,83) 1.410 (35,81)
32 1.650 (41,91) 1.610 (40,89)
40 2.090 (53,09) 2.040 (51,82)
48 2.450 (62,23) 2.390 (60,71)
52 2.650 (67,31) 2.590 (65,79) 4040053 / B 04/95
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MS-011 Falls within JEDEC MS-015 (32 pin only)
58
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS370Cx2x 8-BIT MICROCONTROLLER
SPNS018C - FEBRUARY 1993 - REVISED FEBRUARY 1997
MECHANICAL DATA
NJ (R-PDIP-T**)
40 PIN SHOWN A DIM 40 21 A MAX 1.425 (36,20) 2.031 (51,60) PINS **
PLASTIC SHRINK DUAL-IN-LINE PACKAGE
40
54
0.560 (14,22) MAX
1 0.048 (1,216) 0.032 (0,816)
20
0.200 (5,08) MAX 0.020 (0,51) MIN 0.600 (15,24)
Seating Plane
0.070 (1,78) 0.022 (0,56) 0.014 (0,36) 0.010 (0,25) M
0.125 (3,18) MIN
0- 15 0.010 (0,25) NOM 4040034/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
59
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